The present invention relates to a variable function information processor.
Conventionally, there exists a variable function information processing circuit whose circuit configuration can be changed by being defined. Also, there exists a variable function information processor using the variable function information processing circuit. A logic module constituting the variable function information processing circuit used in the conventional variable function information processor constitutes an information processing circuit for performing desired processing by a method of performing a combinational logic operation by a certain part of an arithmetic circuit in the logic module and performing a sequential operation by another certain part of the arithmetic circuit. Namely, the logic module constituting the conventional variable function information processing circuit is structured to include a part for performing a combinational logic operation and a part for performing a sequential operation different from the part for performing the combinational logic operation.
Therefore, when the logic module is used for a certain combinational logic operation (the part for performing the combinational logic operation is used), the part of the arithmetic circuit for performing the sequential operation is not used, and similarly, when the logic module is used for a certain sequential operation (the part for performing the sequential operation is used), the part of the arithmetic circuit for performing the combinational logic operation is not used. Hence, when a variable function information processor for performing desired processing is structured using the variable function information processing circuit, the resources of the variable function information processor are not effectively exploited, thereby causing waste.
As a logic module to solve this problem, the invention disclosed in Japanese Patent Laid-open No. 9-284124 (hereinafter referred to as xe2x80x9ca conventional examplexe2x80x9d) is given. In the conventional example, a logic module is structured so as to perform a combinational logic operation function of more than 2,200 Boolean algebras or perform a sequential operation function of a D-type latch or D-type flip-flop, and both a combinational circuit and a sequential circuit are formed by using the logic module, whereby a space on a gate array is efficiently used.
The logic module in the conventional example is, however, composed of three two-input multiplexers and three two-input multiplexers with inverting inputs, and uses 42 transistors in total. The smaller the number of transistors constituting one logic module, the more the number of logic modules integrated on one LSI chip becomes, whereby a high-performance and advanced information processor can be realized. Accordingly, it is preferable that the number of transistors constituting a logic module be smaller.
A problem to be solved of the present invention is to provide a variable function information processor which uses a logic module with the further decreased number of transistors to be used in order that logic modules constituting the variable function information processor are increased in number, that is, integrated at a high degree of integration.
Another problem to be solved of the present invention is to realize both a combinational logic circuit and a sequential circuit by the same logic module, whereby the resources of a variable function information processor are effectively exploited.
A variable function information processor of the present invention is characterized by comprising: at least one basic circuit block composed of a two-input arithmetic circuit structured by a two-input exclusive-NOR circuit or a two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal, an inverter for inverting an output signal of the two-input arithmetic circuit, a switching circuit for transmitting an output signal of the inverter or a second signal inputted from a second input terminal as the other input signal to the two-input arithmetic circuit in accordance with a third signal inputted from a third input terminal, and an output terminal capable of outputting at least either the output signal of the two-input arithmetic circuit or the output signal of the inverter; an input terminal group including the first to third input terminals; an output terminal group including the output terminal; and a semiconductor arithmetic circuit electrically connected to the input terminal group, the output terminal group, and the basic circuit block, wherein a function of serving both as a combinational logic circuit for performing a logical operation of the input signals and as a sequential circuit for performing a sequential operation of the input signal according to the input signals inputted from the input terminal group is provided, and through the use of the basic circuit block, in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that the semiconductor arithmetic circuit includes an output switching circuit for selectively outputting any of the input signals inputted from the input terminal group.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a first two-input arithmetic circuit structured by a first two-input exclusive-NOR circuit or a first two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input arithmetic circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the first two-input arithmetic circuit in accordance with a third signal inputted from a third input terminal, the first basic circuit block outputting the output signal of the first two-input arithmetic circuit or the output signal of the first inverter as an output signal of the first basic circuit block, the second basic circuit block includes: a second two-input arithmetic circuit structured by a second two-input exclusive-NOR circuit or a second two-input exclusive-OR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal; a second inverter for inverting an output signal of the second two-input arithmetic circuit; and a second switching circuit for transmitting an output signal of the second inverter or the output signal of the first basic circuit block as the other input signal to the second two-input arithmetic circuit in accordance with a fifth signal inputted from a fifth input terminal, the second basic circuit block outputting the output signal of the second two-input arithmetic circuit or the output signal of the second inverter via a first external output terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the first two-input arithmetic circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a first two-input exclusive-NOR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input exclusive-NOR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the first two-input exclusive-NOR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a second two-input exclusive-NOR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal, for outputting an output signal via a first external output terminal; a second inverter for inverting the output signal of the second two-input exclusive-NOR circuit; and a second switching circuit for transmitting an output signal of the second inverter or the output signal of the first two-input exclusive-NOR circuit as the other input signal to the second two-input exclusive-NOR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the first two-input exclusive-NOR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a two-input exclusive-NOR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input exclusive-NOR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the two-input exclusive-NOR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a two-input exclusive-OR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal; a second inverter for inverting an output signal of the two-input exclusive-OR circuit and outputting an output signal via a first external output terminal; and a second switching circuit for transmitting the output signal of the second inverter or the output signal of the two-input exclusive-NOR circuit as the other input signal to the two-input exclusive-OR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the two-input exclusive-NOR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the two-input exclusive-OR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the two-input exclusive-OR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a two-input exclusive-NOR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal, for outputting an output signal via a first external output terminal; a second inverter for inverting the output signal of the two-input exclusive-NOR circuit; and a second switching circuit for transmitting an output signal of the second inverter or the output signal of the first inverter as the other input signal to the two-input exclusive-NOR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the two-input exclusive-OR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a first two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input exclusive-OR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the first two-input exclusive-OR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a second two-input exclusive-OR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal; a second inverter for inverting an output signal of the second two-input exclusive-OR circuit and outputting an output signal via a first external output terminal; and a second switching circuit for transmitting the output signal of the second inverter or the output signal of the first inverter as the other input signal to the second two-input exclusive-OR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the first two-input exclusive-OR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a first two-input exclusive-NOR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input exclusive-NOR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the first two-input exclusive-NOR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a second two-input exclusive-NOR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal; a second inverter for inverting an output signal of the two-input exclusive-NOR circuit and outputting an output signal via a first external output terminal; and a second switching circuit for transmitting the output signal of the second inverter or the output signal of the first inverter as the other input signal to the second two-input exclusive-NOR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the first two-input exclusive-NOR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a two-input exclusive-NOR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the two-input exclusive-NOR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the two-input exclusive-NOR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a two-input exclusive-OR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal and outputting an output signal via a first external output terminal; a second inverter for inverting the output signal of the two-input exclusive-OR circuit; and a second switching circuit for transmitting an output signal of the second inverter or the output signal of the first inverter as the other input signal to the two-input exclusive-OR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the two-input exclusive-NOR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the two-input exclusive-OR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the other input signal to the two-input exclusive-OR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a two-input exclusive-NOR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal; a second inverter for inverting the output signal of the two-input exclusive-NOR circuit and outputting an output signal via a first external output terminal; and a second switching circuit for transmitting the output signal of the second inverter or the output signal of the two-input exclusive-OR circuit as the other input signal to the second two-input exclusive-NOR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the two-input exclusive-OR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a first and a second basic circuit block are provided, and the first basic circuit block includes: a first two-input exclusive-OR circuit, to which a first signal is inputted as one input signal from a first input terminal; a first inverter for inverting an output signal of the first two-input exclusive-OR circuit; and a first switching circuit for transmitting an output signal of the first inverter or a second signal inputted from a second input terminal as the-other input signal to the first two-input exclusive-OR circuit in accordance with a third signal inputted from a third input terminal, the second basic circuit block includes: a second two-input exclusive-OR circuit, to which a fourth signal is inputted as one input signal from a fourth input terminal, for outputting an output signal via a first external output terminal; a second inverter for inverting the output signal of the second two-input exclusive-OR circuit; and a second switching circuit for transmitting an output signal of the second inverter or-the output signal of the first two-input exclusive-OR circuit as the other input signal to the second two-input exclusive-OR circuit in accordance with a fifth signal inputted from a fifth input terminal, the semiconductor arithmetic circuit transmits a sixth signal inputted from a sixth input terminal or a seventh signal inputted from a seventh input terminal to a second external output terminal in accordance with at least either the output signal of the first two-input exclusive-OR circuit or the output signal of the first inverter, a function of serving both as a combinational logic circuit for performing a full addition operation of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to the input signals inputted from the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that the variable function information processor further comprises a third two-input arithmetic circuit structured by a third two-input exclusive-NOR circuit or a third two-input exclusive-OR circuit, whose output terminal is electrically connected to at least one of the first to seventh input terminals, a function of serving both as a combinational logic circuit for performing an addition operation or a subtraction operation of a set of the input signals and outputting a result of the operation and as a sequential circuit for temporarily holding the input signal to delay the input signal and outputting it according to input signals inputted from input terminals for inputting input signals to the third two-input arithmetic circuit and the first to seventh input terminals is provided, and that in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of-the variable function information processor of the present invention is characterized in that a plurality of the aforementioned variable function information processors are provided and electrically connected to one another directly or via a semiconductor arithmetic circuit, whereby a new input terminal group is formed by a plurality of input terminals through which input signals are allowed to be inputted from the outside to the variable function information processor, and a new output terminal group is formed by a plurality of output terminals through which output signals are allowed to be inputted from the variable function information processor to the outside, a function of serving both as a combinational logic circuit and a sequential circuit according to the input signals inputted from the input terminal group is provided, and that in a semiconductor circuit element group to constitute the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that the variable function information processor comprises: at least one basic circuit block composed of a two-input arithmetic circuit, to which a first signal is inputted as one input signal from a first input terminal, for outputting an operation result of a predetermined logical operation of the first signal and the other input signal or an inverted signal of the other input signal according to the first signal, an inverter for inverting the output signal of the two-input arithmetic circuit, a switching circuit for selectively supplying an output signal of the inverter or a second signal inputted from a second input terminal as the other input signal to the two-input arithmetic circuit in accordance with a third signal inputted from a third input terminal, and an output terminal capable of outputting at least either the output signal of the two-input arithmetic circuit or the output signal of the inverter, the basic circuit block serving both as a combinational logic circuit and as a sequential circuit according to the input signals inputted from the first to third input terminals, and in semiconductor circuit elements to function as the combinational logic circuit and the sequential circuit respectively, sharing a common circuit element between both the circuits.
Another aspect of the variable function information processor of the present invention is characterized in that a plurality of the basic circuit blocks are provided, and that on the occasion of subordinate connection, the output terminal of the basic circuit block in a preceding stage is connected to the second input terminal of the basic circuit block in a subsequent stage.
Another aspect of the variable function information processor of the present invention is characterized in that the two-input arithmetic circuit is a two-input exclusive-NOR circuit or a two-input exclusive-OR circuit.
Another aspect of the variable function information processor of the present invention is characterized in that the basic circuit block functions as an adding circuit or a latch circuit according to the input signal inputted from the first input terminal.
Another aspect of the variable function information processor of the present invention is characterized in that the variable function information processor further comprises: a semiconductor arithmetic circuit for performing predetermined processing in response to a signal inputted; and an external output terminal capable of outputting an output signal of the semiconductor arithmetic circuit, the semiconductor arithmetic circuit performing the predetermined processing in response to at least any one signal of the input signal inputted from the first to third input terminals or an external input terminal, the output signal of the two-input arithmetic circuit, and the output signal of the inverter.
Another aspect of the variable function information processor of the present invention is characterized in that the semiconductor arithmetic circuit includes an output switching circuit for outputting the input signal inputted from the first to third input terminals or the external input terminal according to at least either the output signal of the two-input arithmetic circuit or the output signal of the inverter.